The three dimensional (3D) integration of two or more semiconductor structures may be beneficial in microelectronic applications. For example, 3D integration of microelectronic devices may result in improved electrical performance and power consumption whilst reducing the overall device footprint. See, for example, the publication of P. Garrou et al., 2008, entitled “The Handbook of 3D Integration,” Wiley-VCH.
The 3D integration of semiconductor structures may be achieved by a number of methods, including for example, the attachment of one or more semiconductor structures to a processed semiconductor structure that comprises a plurality of device structures. The attachment of a semiconductor structure to a processed semiconductor structure may be achieved by a number of methods. Upon attaching the semiconductor structure to the processed semiconductor structure, the semiconductor structure may undergo additional processes and may itself be used as a receiving substrate for the attachment of further semiconductor structures. It should also be noted that the 3D integration of semiconductor structures may take place by the attachment of a semiconductor die to another semiconductor die (i.e., die-to-die (D2D)), the attachment of a semiconductor die to a semiconductor wafer (i.e., die-to-wafer (D2W)) as well as the attachment of a semiconductor wafer to another semiconductor wafer (i.e., wafer-to-wafer (W2W)), or a combination thereof.
However, the smoothness and the planarity of each of the structures to be attached to one another, e.g., the attachment surfaces of the processed semiconductor structure and the semiconductor structures, may have an effect on the quality of the completed 3D integrated semiconductor structure. For example, when the 3D integration of a structure comprises a processed semiconductor structure in which semiconductor devices have been processed, such processes may result in rough, non-planar surfaces. Subsequent attachment of a semiconductor structure to the rough, non-planar surfaces of the processed semiconductor structure may result in a poor adhesion between the semiconductor structure and the processed semiconductor structure, which may result in an undesirable separation of the semiconductor structure from the processed semiconductor structure during subsequent processes.
By way of introduction FIGS. 1A-1C illustrate a previously known method for formation of a 3D integrated structure.
FIG. 1A illustrates semiconductor structure 100 comprising processed semiconductor structure 102. The processed semiconductor structure may include conducting region 104, dielectric layer 106 and device substrate 108. Conducting region 104 may comprise a number of subregions, such subregions comprising, for example, barrier subregions and electrode subregions. In addition, conducting region 104 may comprise one or more of a number of materials, such as, for example, cobalt, ruthenium, nickel, tantalum, tantalum nitride, indium oxide, tungsten, tungsten nitride, titanium nitride, copper and aluminum.
Dielectric layer 106 may comprise a number of layers and materials, such as, for example, one or more of polyimides, benzocyclobutene (BCB), boron nitrides, boron carbide nitrides, porous silicates, silicon oxides, silicon nitrides and mixtures thereof (e.g., silicon oxynitride).
Device substrate 108 may comprise one or more device structures 110. For example, the one or more device structures 110 may comprise one or more switching structures (e.g., transistors, etc.), light emitting structures (e.g., laser diodes, light emitting diodes, etc.), light receiving structures (e.g., waveguides, splitters, mixers, photodiodes, solar cells, solar subcells, etc.), and/or microelectromechanical system structures (e.g., accelerometers, pressure sensors, etc.). Device substrate 108 may comprise a number of layers and materials, such as, for example, one or more of silicon, germanium, silicon carbide, III-arsenides, III-phosphides, III-nitrides, III-antimonides, sapphire, quartz and zinc oxide. In some embodiments of the invention, device substrate 108 may comprise one or more of a metal-oxide-semiconductor (CMOS) integrated circuit, a transistor-transistor logic integrated circuit and a NMOS logic integrated circuit.
FIG. 1B illustrates semiconductor structure 115 comprising processed semiconductor structure 102. Processed semiconductor structure 102 may include dielectric layer 106, device substrate 108 and conducting regions 112, which may be defined upon removal of a portion of conducting region 104 (shown in phantom). A portion of conducting region 104 may be removed to produce a plurality of conducting regions 112, wherein the plurality of conducting regions 112 may provide electrical connections between device structures 110 present within device substrate 108. A portion of conducting region 104 may be removed by methods such as, for example, polishing, grinding and in some embodiments of the invention by chemical-mechanical polishing (CMP). Such processes for forming conducting regions 112 may be referred to in the art as “Damascene” methods, and examples of such processes are disclosed in, for example, Joshi et al., “A new Damascene structure for submicrometer wiring,” IEEE Electron Device Letters, Volume 14, No. 3, pages 129-132, 1993.
As illustrated in FIG. 1B the removal of a portion of conducting region 104 may result in the removal of portions of the conducting regions 112 below surface 114 (illustrated by the dashed line) and may also result in the removal of portions of dielectric layer 106. The removal of portions of the conducting regions 112 below surface 114 may be referred to in the art as “dishing,” and may produce a plurality of dished regions 116. The removal of the dielectric layer 106 below surface 114 may be referred to in the art as “erosion,” and may produce a plurality of eroded regions 118. Both the removal of portions of conducting regions 112 and portions of dielectric layer 106 below surface 114 may render a surface 120 non-planar and cause the non-planar surface 120 to have an undesirable surface roughness.
FIG. 1C illustrates semiconductor structure 125, which comprises processed semiconductor structure 102 and semiconductor structure 122. Semiconductor structure 122 may be attached via bonding to processed semiconductor structure 102 at a bonding interface 124 therebetween. As a result of rough non-planar surface 120 of the processed semiconductor structure 102, the bonding interface 124 may be discontinuous, i.e., the bonding interface may comprise bonded and unbonded regions. In addition, the plurality of dished regions 116 and the plurality of eroded regions 118 resulting from processes for removing portions of conducting region 104 may result in a plurality of unbonded regions. Due to a possible high density of unbonded areas between semiconductor structure 122 and processed semiconductor structure 102, the bond strength achieved between the two structures (i.e., between structures 102 and 122) may be insufficient for additional operations, for example, additional operations such as handling and supplementary processing.